One type of memory known in the art is double data rate synchronous dynamic random access memory (DDR SDRAM). In general, DDR SDRAM includes at least one array of memory cells. The memory cells in the array of memory cells are arranged in rows and columns, with the rows extending along an x-direction and the columns extending along a y-direction. Conductive word lines extend across the array of memory cells along the x-direction and conductive bit lines extend across the array of memory cells along the y-direction. A memory cell is located at each cross point of a word line and a bit line. Memory cells are accessed using a row address and a column address.
DDR SDRAM uses a main clock signal and a data strobe signal (DQS) for addressing the array of memory cells and for executing commands within the memory. The clock signal is used as a reference for the timing of commands such as read and write operations, including address and control signals. DQS is used as a reference to latch input data into the memory and output data into an external device.
In a memory array, the read time required to output the data from the array varies from the first column of the array to the last column of the array. Typically, to compensate for this difference in read times, a read timer is used to estimate either the fastest or the slowest read time, usually the slowest read time. The read timer is then used to latch data read from the array between the estimated fastest and slowest read times. The read timer, however, provides only an approximation of the actual read times, which may vary based on the process, temperature, voltage, and other factors. In some cases, variations of these factors may result in the latching of invalid data from the array, especially as the frequency of the data access is increased.